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| ia82527 data sheet can serial communications controller september 16 , 2009 ia 211080504 - 0 6 http://www.innovasic.com customer support: page 1 of 58 ( 888 ) 824 - 4184 ia 82527 serial communications controller can protocol data sheet
ia82527 data sheet can serial communications controller september 16 , 200 9 ia 211080504 - 0 6 http://www.innovasic.com customer support: page 2 of 58 ( 888 ) 824 - 4184 copyright 2009 by innovasic semiconductor, inc. published by innovasic semiconductor, inc. 3737 princeton drive ne, suite 130, albuquerque, n m 87107 miles ? is a trademark innovasic semiconductor, inc. intel is a registered trademark of intel corporation ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 3 of 58 (888) 824 - 4184 table of contents 1. introduction ................................ ................................ ................................ ............................. 6 1.1 general descri ption ................................ ................................ ................................ ....... 6 1.2 features ................................ ................................ ................................ ......................... 7 2. packaging, pin descriptions, and physical dimensions ................................ ......................... 8 2.1 packages and pinouts ................................ ................................ ................................ .... 8 2.1.1 plcc package ................................ ................................ ................................ .. 9 2.1.2 plcc physical dimensions ................................ ................................ ............ 11 2.1.3 pqfp package ................................ ................................ ................................ 12 2.1.4 pqfp physical dimensions ................................ ................................ ............ 14 2.2 pin/signal descriptions ................................ ................................ ............................... 15 3. maximum ratings, thermal characteristics, and dc parameters ................................ ....... 25 4. functional description ................................ ................................ ................................ .......... 28 4.1 hardware architecture ................................ ................................ ................................ 28 4.1.1 can controller ................................ ................................ .............................. 29 4.1.2 message ram ................................ ................................ ................................ 29 4.1.3 i/o ports ................................ ................................ ................................ .......... 30 4.1.4 programmable clock output ................................ ................................ .......... 30 4.2 address map ................................ ................................ ................................ ............... 30 4.3 can message objects ................................ ................................ ................................ 30 5. ac specifications ................................ ................................ ................................ ................. 33 6. innovasic part number cross - re ference ................................ ................................ .............. 53 7. errata ................................ ................................ ................................ ................................ ..... 54 7.1 summary ................................ ................................ ................................ ..................... 54 7.2 detail ................................ ................................ ................................ ........................... 54 8. revision history ................................ ................................ ................................ ................... 57 9. for further information ................................ ................................ ................................ ........ 58 ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 4 of 58 (888) 824 - 4184 list of figures figure 1. plcc package diagram ................................ ................................ ................................ .. 9 figure 2. plcc physical dimensions ................................ ................................ .......................... 11 figure 3. pqfp package diagram ................................ ................................ ................................ 12 figure 4. pqfp physical dimensions ................................ ................................ ........................... 14 figure 5. functional block diagram ................................ ................................ ............................ 28 figure 6 . mosi/miso connection ................................ ................................ ................................ ... 29 figure 7. mode 0 and mode 1: general bus timing ................................ ................................ ... 36 figure 8. mode 0 and mode 1: ready timing for read cycle ................................ ................... 37 figure 9. mode 0 and mode 1: ready timing for write cycle with no write pending ............ 37 figure 10. mode 0 and mode 1: ready timing for write cycle with write active ................... 38 figure 11. mode 2: general bus timing ................................ ................................ ..................... 41 figure 12. mode 3: asynchronous operation, read cycle ................................ ......................... 44 figure 13. mode 3: asynchronous operation, write cycle ................................ ........................ 45 figure 14. mode 3: synchronous operation, read cycle timing ................................ .............. 48 figure 15. mode 3: synchronous operation, write cycle timing ................................ .............. 49 figure 16. serial interface mode: icp = 0 and cp = 0 ................................ ................................ .. 52 figure 17. serial interface mode: icp = 1 and cp = 1 ................................ ................................ .. 52 ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 5 of 58 (888) 824 - 4184 list of tables table 1. plcc pin list ................................ ................................ ................................ ................. 10 table 2. pqfp pin lis t ................................ ................................ ................................ ................. 13 table 3. pin/signal descriptions ................................ ................................ ................................ ... 15 table 4. absolute maximum ratings ................................ ................................ ........................... 25 table 5. thermal characteristics ................................ ................................ ................................ .. 25 table 6. dc parameters ................................ ................................ ................................ ................ 26 table 7. iso physical layer dc parameters ................................ ................................ ................ 27 table 8. address map ................................ ................................ ................................ ................... 31 table 9. message object structure ................................ ................................ ............................... 32 tab le 10. mode 0 and mode 1: general bus and ready timing for 5.0v operation ................. 34 table 11. mode 0 and mode 1: general bus and ready timing for 3.3v operation ................. 35 table 12. mode 2: general bus timing for 5.0v operation ................................ ....................... 39 table 13. mode 2: general bus timing for 3.3v operation ................................ ....................... 40 table 14. mode 3: asynchronous operation timing for 5.0v operation ................................ ... 42 table 15. mode 3: asynchronous operation timing for 3.3v operation ................................ ... 43 table 16. mode 3: synchronous operation timing for 5.0v operation ................................ ..... 46 table 17. mode 3: synchronous operation timing for 3.3v operation ................................ ..... 47 table 18. serial interface mode timing for 5.0v operation ................................ ....................... 50 table 19. serial interface mode timing for 3.3v operation ................................ ....................... 51 table 20. innovasic part number cross - reference ................................ ................................ ...... 53 table 21. revision history ................................ ................................ ................................ ........... 57 ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 6 of 58 (888) 824 - 4184 1. introduction the innov asic semiconductor ia 82527 controller area network (can) serial communications controller is a form , fit, and function replacement for the original intel ? 8 2527 serial communications controller . these devices are produced using innovasics managed ic lifet ime extension system ( miles ?). this cloning technology, which produces replacement ics beyond simple emulations, ensures complete compatibility with the original device, including any undocumented features. additionally, miles ? captures the clone design in such a way that produc tion of the clone can continue even as silicon technology advances. the ia 82527 serial communications controller replaces the obsolete intel 82527 device, allowing users to retain existing board designs, software compilers/assemblers, and emulation tools, thereby avoiding expensive redesign efforts. 1.1 general description can protocol uses a multi - master csma/cr ( carrier sense, multiple access with collision resolution ) bus to transfer message objects between network nodes. the ia82527 support can specificatio n 2.0 part a and b, standard and extended message frames, and has the capability to transmit, receive, and perform message filtering on standard and extended mes sage frames . the ia82527 can store 15 message objects of 8 - byte data length. each message obje ct can be configured as either transmit or receive except for message object 15 , which is receive - only. m essage object 15 also provides a special acceptance mask designed to filter message identifiers that are received. the ia82527 also provide s a progra mmable acceptance mask that allows user s to globally mask any identifier bits of the incoming message. th is global mask can be used for both standard and extended message frames. the ia82527 is capable of operating at 5.0 or 3.3 volts. this datasheet dis cusses both modes of operation. where applicable, characteristics specific to either 3.3 or 5.0 volt operation are identified separately throughout this datasheet. the ia82527 is manufactured in a reliable 5 - volt process technology and is available in 44 - lead plcc or p qfp roh s packages for the automotive temperature range ( - 40c to 125c). ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 7 of 58 (888) 824 - 4184 1.2 features the primary features of the ia82527 are as follows: c an protocol support C specification 2.0, part a and part b C standard id data and remote frames C extended id d ata and remote frames can bus interface C configurable input comparator C configurable output driver C programmable bit rate global mask, programmable C standard message identifier C extended message identifier message objects C 14 transmit/receive buffers C 1 double b uffered receive buffer with programmable mask flexible status interface cpu interface options C 16 - bit multiplexed intel architecture C 8 - bit multiplexed intel architecture C 8 - bit multiplexed non - intel architecture C 8 - bit non - multiplexed non - intel architecture C s erial (spi) i/o ports (2) C 8 - bit C bidirectional flexible interrupt structure programmable clock output a detailed description of the ia82527, including the features listed above, is provided in chapter 4 , functional description . ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 8 of 58 (888) 824 - 4184 2. packaging , pin descriptions , and physical dimensions 2.1 packages and pinouts the innovasic semiconductor ia82527 can serial communications controller is available in the following roh s packages: 44 - pin plastic leaded chip carrier (plcc) , equivalent to original intel plcc package 44 - pin plastic quad flat pack ( p qfp) , equivalent to original intel qfp package ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 9 of 58 (888) 824 - 4184 2.1.1 plcc package the pinout for the plcc package is as shown in figure 1 . the corresponding pinout is provided in table 1 . figure 1 . plcc package diagram ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 10 of 58 (888) 824 - 4184 t able 1 . plcc pin list pin name pin name pin name pin name 1 v cc 12 p2.5 23 v ss1 34 ad12/d4/p1.4 2 a2/ad2/csas 13 p2.4 24 int_n/v cc /2 35 ad11/d3/p1.3 3 a1/ad1/cp 14 p2.3 25 tx1 36 ad10/d2/p1.2 4 a0/ad0/icp 15 p2.2 26 tx0 37 ad9/d1/p1.1 5 ale/as 16 p2.1 27 clkout 38 ad8/d0/p1.0 6 rd_n/e 17 p2.0 28 ready/miso 39 a7/ad7 7 wr_n/wrl_n/r - w_n 18 xtal1 29 reset_n 40 a6/ad6/sclk 8 cs_n 19 xtal2 30 mode1 41 a5/ad5 9 dsack0_n 20 v ss2 31 ad15/d7/p1.7 42 a4/ ad4/mosi 10 wrh_n/p2.7 21 rx1 32 ad14/d6/p1.6 43 a3/ad3/ste 11 int_n/p2.6 22 rx0 33 ad13/d5/p1.5 44 mode0 ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 11 of 58 (888) 824 - 4184 2.1.2 plcc p hysical dimensions the physical dimensions for the plcc are as shown in figure 2 . figure 2 . plcc physical dimensions legend: symbol min nom max a 0.1 650 C 0.1800 a1 0.0200 C C a2 0.1450 C 0.1600 a3 0.0 42 C 0.0 56 b 0.0130 0.0170 0.0210 c 0.0077 C 0. 0 1 5 d 0.6850 C 0.6950 d1 0.6500 C 0.6560 d2 0. 582 C 0. 638 e 0.6850 C 0.6950 e1 0.6500 C 0.6560 e2 0. 582 C 0. 638 n C 44 C n1 C 11 C p C 0.0500 C 7 7 note : controlling dimension in inches. ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 12 of 58 (888) 824 - 4184 2.1.3 p qfp package the pinout for the p qfp package is as shown in figure 3 . the corresponding pinout is provided in table 2 . figure 3 . pqfp package diagram ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 13 of 58 (888) 824 - 4184 table 2 . pqfp pin list pin name pin name pin name pin name 1 wr_n/wrl_n/r - w_n 12 xtal1 23 reset_n 34 a6/ad6/sclk 2 cs_n 13 xtal2 24 mode1 35 a5/ad5 3 dsack0_n 14 v ss2 25 ad15/d7/p1.7 36 a4/ad 4/mosi 4 wrh_n/p2.7 15 rx1 26 ad14/d6/p1.6 37 a3/ad3/ste 5 int_n/p2.6 16 rx0 27 ad13/d5/p1.5 38 mode0 6 p2.5 17 v ss1 28 ad12/d4/p1.4 39 v cc 7 p2.4 18 int_n/v cc /2 29 ad11/d3/p1.3 40 a2/ad2/csas 8 p2.3 19 tx1 30 ad10/d2/p1.2 41 a1/ad1/cp 9 p2.2 20 tx0 31 ad9/d1/p1.1 42 a0/ad0/icp 10 p2.1 21 clkout 32 ad8/d0/p1.0 43 ale/as 11 p2.0 22 ready/miso 33 a7/ad7 44 rd_n/e ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 14 of 58 (888) 824 - 4184 2.1.4 pqfp p hysical dimensions the physical dimensions for the pqfp are as shown in figure 4 . figure 4 . pqfp physical dimensions legend: symbol min nom max n C 44 C n1 C 11 C p C 0.031 C a C C 0.096 a2 C 0.079 C a1 C 0.010 C l 0.019 0.025 0.031 (f) C 0.047 C e 0.478 0.488 0.498 d 0.478 0.488 0.498 e1 0.390 0.394 0.398 d1 0.390 0.394 0.398 c 0.005 0.007 0.009 b 0.0 11 0.014 0.017 ch C 0.030 C 5 C 16 5 C 16 0 C 10 note : controlling dimension in inches. ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 15 of 58 (888) 824 - 4184 2.2 pin /signal descriptions descriptions of the pin and signal functions for the ia82527 serial communications controller ar e provided in table 3 . several of the ia82527 pins have different functions depending on the operating mode of the device. each of the different signals supported by a pin is listed and defined in table 3, indexed alphabetically in the first column of the table. additionally, the name of the pin associated with the signal as well as the pin numbers for both the plcc and pqfp packages are provided in the pin column. if the signal and pin names are the same, no entry is provided in the pin - name column. table 3 . pin/signal descriptions signal pin description name plcc pqfp a0 a0/ad0/icp 4 42 a ddress bits 7 C 0 . input. mode 3. when the ia82527 is configured to operate in the 8 - bit non - multiplexed non - intel architecture mode ( mode 3), these lines provide the 8 - bit address bus input to the device. a1 a1/ad1/cp 3 41 a2 a2/ad2/csas 2 40 a3 a3/ad3/ste 43 37 a4 a4/ad4/mosi 42 36 a5 a5/ad5 41 35 a6 a6/ad6/sclk 40 34 a7 a7/ad7 39 33 ad0 a0/ad0/icp 4 42 a ddress/ d ata bits 15 C 0 . input/output. mode 1. when the ia82527 is configured to operate in the 16 - bit multiplexed intel architecture mode (mode 1), these lines provide the 16 - bit address bus (input) and the 16 - bit data bus (input/output) for the device. ad1 a1/ad1/cp 3 41 ad2 a2/ad2/csas 2 40 ad3 a3/ad3/ste 43 37 ad4 a4/ad4/mosi 42 36 ad5 a5/ad5 41 35 ad6 a6/ad6/sclk 40 34 ad7 a7/ad7 39 33 ad8 ad8/d0/p1.0 38 32 ad9 ad9/d1/p1.1 37 31 ad10 ad10/d2/p1.2 36 30 ad11 ad11/d3/p1.3 35 29 ad12 ad12/d4/p1.4 34 28 ad13 ad13/d5/p1.5 33 27 ad14 ad14/d6/p1.6 32 26 ad15 ad15/d7/p1.7 31 25 ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 16 of 58 (888) 824 - 4184 table 3 . pin/signal descriptions (continued) signal pin description name plcc pqfp ale ale/as 5 43 a ddress l atch e nable. input. active high. mode 0 and mode 1. when the ia82527 is configured to operate in either the 8 - bit multiplexed intel architecture mode (mode 0) or the 16 - bit multiplexed intel architecture mode (mode 1), this signal latches the address into the device during the address phase of the bus cycle . as ale/as 5 43 a ddress s trobe. input. active high. mode 2. when the ia82527 is configured to operate in the 8 - bit multiplexed non - intel architecture mode (mode 2), this signal latches the address into the device during the address phase of the bus c ycle. if the ia82527 is con figured to operate in mode 3 (8 - bit non - multiplexed non - intel architecture), this pin must be tied high. clkout clkout 27 21 cl oc k out . output (push - pull). this output provides a programmable clock frequency. the frequency i s set via the clockout register (1fh) and can range from the frequency of the xtal (crystal) input to xtal/ n , where n can be an integer value from 2 through 15. this output allows the ia82527 to clock other devices such as the host cpu. for 3.3v operation the crystal or external oscillator must run at < =12 mhz to produce clock output. cp a1/ad1/cp 3 41 c lock p hase. input. serial interface mode. when this input is a logic 0, data is sampled on the rising edge of sclk . when this input is a logic 1, data is sampled on the falling edge of sclk . cs_n cs_n 8 2 c hip s elect. input. active low (modes 0 C 3); selectable active level (serial interface mode). when the ia82527 is configured to operate in one of the parallel interface modes (modes 0 C 3) or the seri al interface mode, this input, during its active state, selects the device allowing cpu access. for serial interface mode operation, the active state is selectable (i.e., either high or low) via the ia8257 csas pin. csas a2/ad2/csas 2 40 c hip s elect a cti ve s tate. input. serial interface mode. when this input is a logic 0, the cs_n input is confi gured to function active low. when this input is a logic 1, the cs_n input is configured to function active high. ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 1 7 of 58 (888) 824 - 4184 table 3. pin/signal descriptions (continue d) signal pin description name plcc pqfp d0 ad8/d0/p1.0 38 32 d ata bits 7 C 0 . input/output. mode 3. when the ia82527 is configu red to operate in the 8 - bit non - multiplexed non - intel architecture mode (mode 3), these lines provide the 8 - bit data bus to the device. d1 ad9/d1/p1.1 37 31 d2 ad10/d2/p1.2 36 30 d3 ad11/d3/p1.3 35 29 d4 ad12/d4/p1.4 34 28 d5 ad13/d5/p1.5 33 27 d6 ad14/d6/p1.6 32 26 d7 ad15/d7/p1.7 31 25 dsack0_n dsack0_n 9 3 d ata and s ize ack nowledge 0 . output. active low (op en drain with active pull - up). mode 3 (asynchronous operation). when the ia82527 is configured to operate i n the 8 - bit non - multiplexed non - intel architecture mode (mode 3), this signal functions as follows: when the cpu reads from the ia82527, dsack0_n active low indicates that the data is valid; when the cpu writes to the ia82527, dsack0_n active low indicates that the data has been received. note : the active pull - up circuitry drives dsack0_n high for 10ns to raise it to a 3.0v voltage level. after t hat , an external pull up is required to pull dsack0_n the remainder of the way to v ss . e rd_n/e 6 44 e nable. input. active high. mode 3 (synchronous). when the ia82527 is configured to operate in the 8 - bit non - multiplexed non - intel architecture mode ( mode 3), this signal functions as follows: when the cpu reads from or writes to the ia82527, e active high indicates that the address is valid. icp a0/ad0/icp 4 42 i dle c lock p olarity. input. serial interface mode. when this input is a logic 0, the po larity for the idle state of sclk is low. when this input is a logic 1, the polarity for the idle state of sclk is high. ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 18 of 58 (888) 824 - 4184 table 3. pin/signal descriptions (continued) signal pin description name plcc pqfp int_n int_n/ v cc /2 24 18 int errupt. output (open collector). active low. on the ia82527, two pins can provide the interrupt ( int_n ) output; however, depending on the setting of the mux bit in the cpu interface register (02h), only one of the pins will serve as the source of int_n as follows: plc c package: C when the mux bit of the cpu interface register is 0, pin 24 functions as the int_n output and pin 11 functions as p2.6 . C when the mux bit of the cpu interface register is 1, pin 11 functions as the int_n output and pin 24 functions as v cc /2. pqf p package: C when the mux bit of the cpu interface register is 0, pin 18 functions as the int_n output and pin 5 functions as p2.6 . C when the mux bit of the cpu interface register is 1, pin 5 functions as the int_n output and pin 18 functions as v cc /2. int_ n/p2.6 11 5 miso ready/miso 28 22 m aster i n s lave o ut. output (open drain). serial interface mode. when the ia82527 is configured to operate with a serial interface, miso is the serial data output. ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 19 of 58 (888) 824 - 4184 table 3. pin/signal descriptions (continued) signa l pin description name plcc pqfp mode0 mode0 44 38 mode n (n = 1 or 0 ). input. the logic levels at the mode0 and mode1 inputs determine the operating mode (i.e., interface type) of the ia82527 as follows: mode1 mode0 interface type 0 0 8 - bit multip lexed intel 0 1 16 - bit multiplexed intel 1 0 8 - bit multiplexed non - intel 1 1 8 - bit non - multiplexed non - intel the mode1 and mode0 inputs are also used to establish the serial interface mode as follows: when the ia82527 is reset, if mode1 = 0 mode0 = 0 rd_n = 0 wr_n = 0 the serial interface mode will be selected. the mode1 and mode0 pins are internally connected to weak pull - downs. these pins will be pulled low during reset if unconnected. following reset, these pins will float. mode1 mode1 30 24 mosi a4/ad4/mosi 42 36 m aster o ut s lave i n. input. serial interface mode. when the ia82527 is configured to operate with a serial interface, mosi is the serial data input. ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 20 of 58 (888) 824 - 4184 table 3. pin/signal descriptions (continued) signal pin description name plcc pqfp p1.0 ad8/d0/p1.0 38 32 p ort 1 , bit n (n = 7 C 0 ). input/output (general - purpose). mode 0, mode 2, and serial interface mode. port 1 bits p1.7 C p1.0 can be individually programmed as inputs or outputs. programming is accomplished by writing to the p1conf register (9fh). the 8 bits of the p1conf register, p1conf7 C p1conf0, correspond directly to pins p1.7 C p1.0 . writing a 0 to a bit in the p1conf register causes the corresponding pin to be configured as a high - impedance input. writing a 1 to a b it in the p1conf register causes the corresponding pin to be configured as a push - pull output. all port 1 pins have weak pull - ups until the port is configured by writing to the p1conf register. the default value of the p1conf register following a reset i s 00h. data is read from port 1 via the p1in register (bfh). a logic 0 for any bit in this register means that a logic 0 was read from the corresponding pin; a logic 1 for any bit means that a logic 1 was read from the corresponding pin. the default val ue of the p1in register following a reset is ffh. data is written to port 1 via the p1out register (dfh). writing a logic 0 to any bit in this register means that a logic 0 is written to the corresponding pin; writing a logic 1 to any bit means that a lo gic 1 is written to the corresponding pin. the default value of the p1out register following a reset is 00h. p1.1 ad9/d1/p1.1 37 31 p1.2 ad10/d2/p1.2 36 30 p1.3 ad11/d3/p1.3 35 29 p1.4 ad12/d4/p1.4 34 28 p1.5 ad13/d5/p1.5 33 27 p1.6 ad14/d6/p1. 6 32 26 p1.7 ad15/d7/p1.7 31 25 ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 21 of 58 (888) 824 - 4184 table 3. pin/signal descriptions (continued) signal pin description name plcc pqfp p2.0 p2.0 17 11 p ort 2 , bit n (n = 7 C 0 ). input/output. port 2 bits p2.7 C p2.0 , can be individually programmed as inputs or outputs . programming is accomplished by writing to the p2conf register (afh). the 8 bits of the p2conf register, p2conf7 C p2conf0, correspond directly to pins p2.7 C p2.0 . writing a 0 to a bit in the p2conf register causes the corresponding pin to be configured a s a high - impedance input. writing a 1 to a bit in the p2conf register causes the corresponding pin to be configured as a push - pull output. all port 2 pins have weak pull - ups until the port is configured by writing to the p2conf register. the default val ue of the p1conf register following a reset is 00h. data is read from port 2 via the p2in register (cfh). a logic 0 for any bit in this register means that a logic 0 was read from the corresponding pin; a logic 1 for any bit means that a logic 1 was read from the corresponding pin. the default value of the p2in register following a reset is ffh. data is written to port 2 via the p2out register (efh). writing a logic 0 to any bit in this register means that a logic 0 is written to the corresponding pin; writing a logic 1 to any bit means that a logic 1 is written to the corresponding pin. the default value of the p2out register following a reset is 00h. two bits of port 2 (p2.7 and p2.6) have alternate functions based on cpu interface mode. s ee section 4.1. 3 i/o ports . p2.1 p2.1 16 10 p2.2 p2.2 15 9 p2.3 p2.3 14 8 p2.4 p2.4 13 7 p2.5 p2.5 12 6 p2.6 int_n/p2.6 11 5 p2.7 wrh_n/p2.7 10 4 rd_n rd_n/e 6 44 r ea d . input. active low. mode 0 and mode 1. when rd_n is asserted (low), it causes the ia82527 to drive the data from the location being read onto the data bus. ready ready/miso 28 22 ready . output (open drain). active high. mode 0 and mode 1. when ready is asserted (high), it signals the completion of a bus cycle. the ready output is provided to force system cpu wait states as required. ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 22 of 58 (888) 824 - 4184 table 3. pin/signal descriptions (continued) signal pin description name plcc pqfp reset_n reset_n 29 23 reset . input. active low. when the reset_n signal is asserted (low), the ia82527 is initialized. there are two reset situations: cold reset is a power - on reset. as v cc is driven to a valid level (power on), the reset_n signal must be driven low for a minimum of 1 ms measured from a valid v cc level. no fa lling edge on the reset_n pin is required during a cold reset. for warm reset, v cc remains at a valid level (i.e., power is already on and remains on) while reset_n is driven low for a minimum of 1 ms. r - w_n wr_n/wrl_n/r - w_n 7 1 r ead - w rite. input. acti ve high (read) - active low (write). mode 2 and mode 3. when r - w_n is high, it signals a read cycle. when r - w_n is low, it signals a write cycle. rx0 rx0 22 16 receive ( rx ), lines 0 and 1 . input. pins rx0 and rx1 are the inputs to the ia82527 from the can bus lines. these pins connect internally to the receiver input comparator. serial data from the can bus can be received using both rx0 and rx1 or by using only rx0 as follows: when the coby bit in the bus configuration register (2fh) is a 0, rx0 and rx1 are connected to the input comparator rx0 is connected to the non - inverting input and rx1 is connected to th e inverting input ) . a recessive level is read when rx0 > rx1 . a dominant level is read when rx1 > rx0 . when the coby bit in the bus configu ration register (2fh) is a 1, input comparison is disabled, and rx0 , which is still connected to the non - inverting input of the comparator, is the can bus line input. for this configuration, the dcr0 bit of the bus configuration register must be a 0. aft er a cold reset (power on), the default configuration is the use of both rx0 and rx1 for the can bus input. rx1 rx1 21 15 sclk a6/ad6/sclk 40 34 s erial cl oc k . input. serial interface mode. the sclk pin is the serial clock input to the ia82527 (slave device). the clock signal is provided by the master device. ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 23 of 58 (888) 824 - 4184 table 3. pin/signal descriptions (continued) signal pin description name plcc pqfp ste a3/ad3/ste 43 37 s ynchronization t ransmission e nable. input. serial interface mode. the logic leve l at the ste pin enables the transmission of the synchronization bytes through the ia82527 miso pin while the master device transmits the address and control byte as follows: when a logic 0 is placed on the ste pin, the synchronization bytes sent through the miso pin are 00h and 00h. when a logic 1 is placed on the ste pin, the synchronization bytes sent through the miso pin are aah and 55h. the ia82527 sends the synchronization bytes after the cs_n signal has been asserted tx0 tx0 26 20 transmit ( tx ), lines 0 and 1 . output (push - pull). pins tx0 and tx1 are the outputs from the ia82527 to the can bus lines. during a recessive bit, tx0 is high and tx1 is low. during a dominant bit, tx0 is low and tx1 is high. tx1 tx1 25 19 v cc v cc 1 39 power ( v cc ) . this pin provides power for the ia82527 device. it must be connected to a +5v dc power source. v cc /2 int_n/ v cc /2 24 18 reference voltage, iso physical layer ( v cc /2 ). output. the v cc /2 pin provides a reference voltage for the iso low - speed physical layer: 2.38v dc (minimum) to 2.60v dc (maximum) (v cc = +5.0v; i out 75 a) 1.46v dc (minimum) to 1.688v dc (maximum) (v cc = +3.3v; i out 75 a) this pin only functions as v cc /2 when the mux bit of the cpu interface register (02h) is 1. v ss1 v ss1 23 17 ground, digital ( v ss1 ). this pin provides the digital ground (0v) for the ia82527. it must be connected to a v ss board plane. v ss2 v ss2 20 14 ground, analog ( v ss2 ). this pin provides the ground (0v) for the ia82527 analog comparator. it must be connected to a v ss board plane. wr_n wr_n/wrl_n/r - w_n 7 1 wr ite. input . active low. mode 0. when wr_n is asserted (low), it signals a write cycle. ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 24 of 58 (888) 824 - 4184 table 3. pin/signal descriptions (continued) signal pin description name plcc pqfp wrh_n wrh_n/p2.7 10 4 wr ite h igh byte. input. active low. mode 1. when wrh_n is as serted (low), it signals a write cycle for the high byte of data (bits 15 C 8). wrl_n wr_n/wrl_n/r - w_n 7 1 wr ite l ow byte. input. active low. mode 1. when wrl_n is asserted (low), it signals a write cycle for the low byte of data (bits 7 C 0). xtal1 xtal 1 18 12 crystal ( xtal ) 1 . input. the xtal1 pin is the input connection for an external crystal that drives the ia82527 internal oscillator. (when an external crystal is used, it is connected between this pin and the xtal2 pin see next table entry.) if an external oscillator or clock source is used to drive the ia82527 instead of a crystal, the xtal1 pin is the input for this clock source. xtal2 xtal2 19 13 crystal ( xtal ) 2 . output (push - pull). the xtal2 pin is the output connection for an external cr ystal that drives the ia82527 internal oscillator. (when an external crystal is used, it is connected between this pin and the xtal1 pin see previous table entry.) if an external oscillator or clock source is used to drive the ia82527 instead of a crysta l, xtal2 must be left unconnected (i.e., must be floated). additionally, the xtal2 output must not be used as a clock source for other system components. ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 25 of 58 (888) 824 - 4184 3. maximum ratings, thermal characteristics, and dc parameters for the innovasic semiconductor ia8252 7 serial communications controller, the absolute maximum ratings, thermal characteristics, and dc parameters are provided in tab les 4 through 6 , respectively. additionally, the dc parameters of the iso physical layer are provided in table 7 . table 4 . absolute maximum ratings parameter rating storage temperature ?55c to +150c case temperature under bias ?40c to +125c supply voltage with respect to v ss ?0.3v to +7.0v voltage on pins other than supply with respect to v ss ?0.3v to v dd +0.3v table 5 . thermal characteristics symbol characteristic value units t a ambient temperature - 40 c to 12 5 c c p d power dissipation mhz icc v/1000 w ja 44 - pin plcc package 3 0 c/w 44 - pin pqfp package 38.4 t j average junction temperature t a + (p d ja ) c ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 26 of 58 (888) 824 - 4184 table 6 . dc parameters symbol parameter min max units notes v cc supply voltage 3.0 5.5 v C v il voltage, input low C 0.8 v all pins except xtal1, rx0 for comparator bypass mode v il1 voltage, input low C 0.3*v cc v xtal1, rx0 for comparator bypassed v ih voltage, input high 2.4 C v reset_n hysteresis = 200mv all pins except xtal1, rx0 for comparator bypass mode v ih1 voltage, input high 0.7* v cc C v xtal1, rx0 for comparator bypa ssed v ol voltage, output low C 0.45 v is o physical layer dc parameters ( see table 7 ) . a ll pins except tx0, tx1, xtal2 , i ol = 1.6 ma . v oh voltage, output high v cc ? 0.8 C v iso physical layer dc parameters tx0, tx1, xtal2 ( see table 7 ) . clkout i oh = ?80 a. all other i oh pins = ?200 a . i leak input leakage current C 10 a v ss < v in < v cc c in pin capacitance C 10 pf f crystal = 1 khz i cc supply current C 3 ma /mhz f crystal = 16 mhz, all pins are driven to v ss or v cc i sleep - e sleep current C 800 a v cc /2 enabled, no load i sleep - d sleep current C 150 v cc /2 disabled i pd power - down current C 25 xtal1 clocked, all pins driven to v ss or v cc ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 27 of 58 (888) 824 - 4184 table 7 . iso physical layer dc parameters signal parameter min max units notes rx0 & rx1, tx0 & tx1 input voltage ?0.5 v cc + 0.5 v C common mode range v ss + 1.0 v cc ? 1.0 v C differential input threshold 100 C mv C delay 1 : receive comparato r input delay + tx0/tx1 output delay C 60 (@5.0v) 110 (@3.3v) n s ns load on tx0/tx1 = 100 pf, rx0/rx1 differential = +100 mv to ?100 mv delay 2 : rx0 pin delay (comparator bypassed) + tx0/tx1 output delay C 50 (@5.0v) 60 (@3.3v) n s ns load on tx0/tx1 = 100 pf source current on tx0, tx1 ?10 C ma v out = v cc ? 1.0 v sink current on tx0, tx1 10 C ma v out = 1.0 v input hysteresis for rx0/rx1 C 0 v C v cc /2 reference voltage 2.38 2.62 v i out 75 a, v cc = 5.0 v 1.46 1.688 v i out 75 a, v cc = 3.3 v all ratings listed are for the temperature range t a = ?40c to +125c (v cc = 5v 10%) or (v cc = 3.0 - 3.6v) . ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 28 of 58 (888) 824 - 4184 4. functional description 4.1 hardware architecture a block diagram of the ia 82527 can serial communications c ontroller is shown in figure 5 . the pr imary architectural features of the device are as follows: can controller message ram cpu interface i/o ports programmable clock output these features are briefly described in the following subsections. figure 5 . functional bloc k diagram c p u i n t e r f a c e r x 0 r x 1 c a n c o n t r o l l e r { { t x 0 t x 1 m e s s a g e r a m p r o g r a m m a b l e c l o c k i n t e r n a l r e g i s t e r s m o d e 1 } m o d e s e l e c t c l k o u t p o r t 1 p o r t 2 a d d r e s s / d a t a b u s c o n t r o l b u s r e c e i v e t r a n s m i t p o r t 1 i / o p o r t 2 i / o m o s i m i s o m o d e 0 s e r i a l i n t e r f a c e ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 29 of 58 (888) 824 - 4184 4.1.1 can controller the can c ontroller block of the ia82527 supports the interface to the can bus via the rx0, rx1, tx0, and tx1 lines. the can controller manages the transceiver logic, error management logic , and the message objects, controlling th e data stream between the message ram (parallel data) and the can b us (serial data). 4.1.2 message ram the message ram block of the ia82527 provides the interface buffer between the system cpu and the can b us. the ia 82527 message ram provides stor age for 15 me ssage objects of 8 - byte data length. the message ram is dual port ram allowing the cpu and the can controller simultaneous access to the message ram. 4.1 .3 cpu interface the ia 82527 is can be interfac ed to many commonly used microcontrollers. there are four parallel interface options and a serial interface option. different interface options, or modes , are selected using interface mode pins , mode1 and mode0. the parallel interface modes that can be selected are as follows: 8 - bit intel multiplexed a ddres s and data buses 16 - bit intel multiplexed addr ess and data buses 8 - bit non - intel multiplexed address and data buses 8 - bit non - multiplexed addres s and data buses the serial interface mode is fully compatible with the motorola ? spi protocol and will interf ace to most commonly used serial interfaces. the serial interface is implemented in slave mode only, and responds to the master using the specially designed serial interface protocol. the serial interface mode interconnec tion scheme is shown in figure 6 . figure 6 . mosi / miso connection m o s i m i s o s c l k c s m o s i m i s o s c l k c s _ n i a 8 2 5 2 7 ( s l a v e ) c p u ( m a s t e r ) ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 30 of 58 (888) 824 - 4184 4.1.3 i/o ports the ia82527 contains t wo 8 - bit general purpose input output (gpio) ports . each gpio port is selectable or programmable as either an input or an output. cpu interface modes may use some of the gpio pins or signals, precluding their use as gpio. s ix bits of gpio port 2 (p2.5 to p2.0) are always available as gpio. gpio port 2 bits 6 and 7 (p2.6 and p2.7) have alternate functions as the alternate source for int_n and as the wrh_n input fo r cpu mode 2 and may be available as gpio depending on the cpu mode. gpio port 1 is available for u se as gpio in cpu modes 0, 2, and spi and is not available in cpu modes 1 and 3. 4.1.4 programmable clock output using an oscillator, clock divider register , and a driver circuit , the ia82527 provides a programmable clock output . the output frequency range available is from the ex ternal crystal frequency to that frequency divided by 15. the clock output allows the ia82527 to drive other devices such as the host cpu. the slew rate of the clkout signal is selectable via the clkout register (1fh). 4.2 address map the ia82527 includes 256 8 - bit locations that provide device configuration registers and message storage. the address map is shown in table 8 . 4.3 can message ob jects each can message object has a unique identifier and can be configured as either transmit or receive , except for message object 15 . messa ge object 15 is a double - buffered receive - only buffer with a special mask design to allow select groups of differ ent message identifiers to be received. each message object contains registers for control and status bits. all message objects have separate transmit and receive interrupts and status bits that allow the host cpu to determine when a message frame has b een sent or received. the ia 82527 implements a global masking feature that allows the user to globally mask any identifier bits of the incoming message. this mask is programmable, which permits application - specific message identification. the message obj ect structure is shown in table 9 . ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 31 of 58 (888) 824 - 4184 table 8 . address map address register/message 00h control register 01h status register 02h cpu interface register 03h reserved 04 C 05h high - speed read register 06 C 07h global mask standard 0 8 C 0bh global mask extended 0c - 0fh message 15 mask 10 C 1eh message 1 1fh clkout register 20 C 2eh message 2 2fh bus configuration register 30 C 3eh message 3 3fh bit timing register 0 40 C 4eh message 4 4fh bit timing register 1 50 C 5eh message 5 5fh int errupt register 60 C 6eh message 6 6fh reserved 70h C 7eh message 7 7fh reserved 80 C 8eh message 8 8fh reserved 90 C 9eh message 9 9fh p1conf register a0 C aeh message 10 afh p2conf register b0 C beh message 11 bfh p1in register c0 C ceh message 12 cfh p2 in register d0 C deh message 13 dfh p1out register e0 C eeh message 14 efh p2out register f0 C feh message 15 ffh serial reset address register ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 32 of 58 (888) 824 - 4184 table 9 . message object structure offset (base address +n) message component +0 con trol register 0 +1 control register 1 +2 arbitration register 0 +3 arbitration register 1 +4 arbitration register 2 +5 arbitration register 3 +6 message configuration register +7 data byte 0 +8 data byte 1 +9 data byte 2 +10 data byte 3 +11 data byte 4 +12 data byte 5 +13 data byte 6 +14 data byte 7 ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 33 of 58 (888) 824 - 4184 5. ac specifications the ac characteristics of the ia82527 are provided in the figures and tables of this chapter. the ia82527 can be configured to operate in the following parallel and serial cp u interface modes: mode 0: 8 - bit multiplexed intel architecture mode 1: 16 - bit multiplexed intel architecture mode 2: 8 - bit multiplexed non - intel architecture mode 3: 8 - bit non - multiplexed non - intel architecture serial interface mode the ac characteris tics of these modes in operation are provided as follows: mode 0 and mode 1 : gener al bus timing ( table s 10 and 11 / figure 7 ) mode 0 and mode 1 : ready timing f or read cycle (table 10 and 11 / figure 8 ) mode 0 and mode 1 : ready timing for write cycle with no write pending (table 10 and 11 / figure 9 ) mode 0 and mode 1 : ready timing for write cycle with write pending (table 10 and 11 / figure 10 ) mode 2 : gener al bus timing ( table 12 and 13 / figure 11 ) mode 3: asynchronous operation , read cycle ( table 14 and 15 / f igure 12 ) mode 3: asynchronous operation, write cycle (table 14 and 15 / figure 13 ) mode 3: synchronous operation , read cycle ( table 16 and 17 / figure 14 ) mode 3: synchronous operation, write cycle (table 16 and 17 / figure 15 ) serial interface mode : icp = 0 and cp = 0 ( table 18 and 19 / figure 16 ) serial interface mode: icp = 1 and cp = 1 ( table 18 and 19 / figure 17 ) ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 34 of 58 (888) 824 - 4184 table 10 . mode 0 and mode 1 : general bus and ready timing for 5.0v operation symbol parameter minimum maximum 1/t xt al oscillator frequency 8 mhz 16 mhz 1/t sclk system clock frequency 4 mhz 10 mhz 1/t mclk memory clock frequency 2 mhz 8 mhz t avll address valid to ale low 7.5 ns C t llax address hold after ale low 10 ns C t lhll ale high time 30 ns C t llrl ale low to rd_n low 20 ns C t clll cs_n low to ale low 10 ns C t qvwh data setup to wr_n or wrh_n high 27 ns C t whqx input data hold after wr_n or wrh_n high 10 ns C t wlwh wr_n or wrh_n pulse width 30 ns C t whlh wr_n or wrh_n high to next ale high 8 ns C t whch wr _n or wrh_n high to cs_n high 0 ns C t rlrh rd_n pulse width . this time is long enough to initiate a double read cycle by loading the high speed registers (04h, 05h), but is too short to read from 04h and 05h (see t rldv ). 40 ns C t rldv rd_n low to data v alid ( only for registers 02h, 04h, 05h) 0 ns 55 ns t rldv1 rd_n low data to data valid (for all registers except 02h, 04h, 05h) for read cycle without a previous write a C 1.5 t mclk + 100 ns t rldv1 rd_n low data to data valid (for all registers except 02h, 04h, 05h) for read cycle with a previous write C 3.5 t mclk + 100 ns t rhdz data float after rd_n high 0 ns 45 ns t clyv cs_n low to ready setup (load capacitance on the ready output = 50 pf, v ol = 1.0 v) C 32 ns cs_n low to ready setup (load capacitance on the ready output = 50 pf, v ol = 0.45 v) C 40 ns t wlyz wr_n or wrh_n low to ready float for a write cycle if no previous write is pending C 145 ns hyz end of last write to ready float for a write cycle if a previous write cycle is active b C 2 t mclk + 100 ns t rlyz rd_n low to ready float (for all registers except 02h, 04h, 05h) for read cycle without a previous write a C 2 t mclk + 100 ns t rlyz rd_n low to ready float (for all registers except 02h, 04h, 05h) for read cycle with a previous write C 4 t mcl k + 100 ns t whdv wr_n or wrh_n high to output data valid on port 1 or port 2 t mclk 2 t mclk + 500 ns t copo clkout period ( cd v is the value loaded in the clkout register representing the clkout divisor ) (cd v + 1) t osc C t chcl clkout high period ( cd v is the value loaded in the clkout register representing the clkout divisor ) (cd v + 1) ? t osc C 10 (cd v + 1) ? t osc + 15 a a Dread cycle without a previous write is where a read cycle follows a write cycle and there is greater than 2 t mclk between the ris ing edge of wr_n or wrh_n and the falling edge of rd_n. b a D previous write cycle is active is where the rising edge of wr_n or wrh_n for t he second write is less than 2 t mclk after the rising edge of wr_n or wrh_for the first write. ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 35 of 58 (888) 824 - 4184 table 11 . mode 0 and mode 1 : general bus and ready timing for 3.3v operation symbol parameter minimum maximum 1/t xtal oscillator frequency 8 mhz 16 mhz 1/t sclk system clock frequency 4 mhz 10 mhz 1/t mclk memory clock frequency 2 mhz 8 mhz t avll ad dress valid to ale low 7.5 ns C t llax address hold after ale low 10 ns C t lhll ale high time 30 ns C t llrl ale low to rd_n low 20 ns C t clll cs_n low to ale low 10 ns C t qvwh data setup to wr_n or wrh_n high 27 ns C t whqx input data hold after wr_n o r wrh_n high 10 ns C t wlwh wr_n or wrh_n pulse width 30 ns C t whlh wr_n or wrh_n high to next ale high 8 ns C t whch wr_n or wrh_n high to cs_n high 0 ns C t rlrh rd_n pulse width . this time is long enough to initiate a double read cycle by loading the high speed registers (04h, 05h), but is too short to read from 04h and 05h (see t rldv ). 40 ns C t rldv rd_n low to data valid (only for registers 02h, 04h, 05h) 0 ns 7 5 ns t rldv1 rd_n low data to data valid (for all registers except 02h, 04h, 05h) for rea d cycle without a previous write a C 1.5 t mclk + 100 ns t rldv1 rd_n low data to data valid (for all registers except 02h, 04h, 05h) for read cycle with a previous write C 3.5 t mclk + 100 ns t rhdz data float after rd_n high 0 ns 50 ns t clyv cs_n low to re ady setup (load capacitance on the ready output = 50 pf, v ol = 1.0 v) C 32 ns cs_n low to ready setup (load capacitance on the ready output = 50 pf, v ol = 0.45 v) C 40 ns t wlyz wr_n or wrh_n low to ready float for a write cycle if no previous write is p ending C 145 ns hyz end of last write to ready float for a write cycle if a previous write cycle is active b C 2 t mclk + 100 ns t rlyz rd_n low to ready float (for all registers except 02h, 04h, 05h) for read cycle without a previous write a C 2 t mclk + 100 ns t rlyz rd_n low to ready float (for all registers except 02h, 04h, 05h) for read cycle with a previous write C 4 t mclk + 100 ns t whdv wr_n or wrh_n high to output data valid on port 1 or port 2 t mclk 2 t mclk + 500 ns t copo clkout period ( cd v is the v alue loaded in the clkout register representing the clkout divisor ) (cd v + 1) t osc C t chcl clkout high period ( cd v is the value loaded in the clkout register representing the clkout divisor ) (cd v + 1) ? t osc C 10 (cd v + 1) ? t osc + 15 a a Dread cycl e without a previous write is where a read cycle follows a write cycle and there is greater than 2 t mclk between the rising edge of wr_n or wrh_n and the falling edge of rd_n. b a D previous write cycle is active is where the rising edge of wr_n or wrh_n f or t he second write is less than 2 t mclk after the rising edge of wr_n or wrh_for the first write. ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 36 of 58 (888) 824 - 4184 figure 7 . mode 0 and mode 1 : general bus timing ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 37 of 58 (888) 824 - 4184 figure 8 . mode 0 and mode 1 : ready timing fo r read cycle figure 9 . mode 0 and mode 1 : ready timing for write cycle with no write pending ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 38 of 58 (888) 824 - 4184 figure 10 . mode 0 and mode 1 : ready timing for write cycle with write active ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 39 of 58 (888) 824 - 4184 table 12 . mode 2 : general bus timing for 5.0v operation symbol parameter minimum maximum 1/t xtal oscillator frequency 8 mhz 16 mhz 1/t sclk system clock frequency 4 mhz 10 mhz 1/t mclk memory clock frequency 2 mhz 8 mhz t avsl address valid to as lo w 7.5 ns C t slax address hold after as low 10 ns C t eldz data float after e low 0 ns 45 ns t ehdv e high to data valid for registers 02h, 04h, 05h 0 ns 45 ns e high to data valid (all registers except for 02h, 04h, 05h) for read cycle without a previou s write a C 1.5 t mclk + 100 ns e high to data valid (all registers except for 02h, 04h, 05h) for read cycle with a previous write C 3.5 t mclk + 100 ns t qvel data setup to e low 30 ns C t elqx input data hold after e low 20 ns C t eldv e low to output dat a valid on port 1/2 t mclk 2 t mclk + 500 ns t ehel e high time 45 ns t e l el end of previous write (last e low) to e low for write cycle 2 t mclk t shsl as high time 30 ns C t rseh setup time of r - w_n to e high 30 ns C t sleh as low to e high 20 ns C t clsl cs_n low to as low 20 ns C t elch e low to cs_n high 0 ns C t copd clkout period (cd v is the value loaded in the clkout register representing the clkout divisor ) (cd v + 1) t osc t chcl clkout high period (cd v is the value loaded in the clkout register re presenting the clkout divisor ) (cd v + 1) ? t osc C 10 (cd v + 1) ? t osc + 15 a a Dread cycle without a previous write is where a read cycle follows a write cycle and where the falling edge of e for the write and the rising edge of e for the read are sep arated by at least 2 t mclk . ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 40 of 58 (888) 824 - 4184 table 13 . mode 2 : general bus timing for 3.3v operation symbol parameter minimum maximum 1/t xtal oscillator frequency 8 mhz 16 mhz 1/t sclk system clock frequency 4 mhz 10 mhz 1/t mclk memory clock frequency 2 mhz 8 mhz t avsl address valid to as low 7.5 ns C t slax address hold after as low 10 ns C t eldz data float after e low 0 ns 45 ns t ehdv e high to data valid for registers 02h, 04h, 05h 0 ns 45 ns e high to data valid (all registers except for 02h, 04h, 05h) for read cycle without a previous write a C 1.5 t mclk + 100 ns e high to data valid (all registers except for 02h, 04h, 05h) for read cycle with a previous write C 3.5 t mclk + 100 ns t qvel data setup to e low 30 ns C t elqx input data hold after e low 20 ns C t eldv e low to output data valid on port 1/2 t mclk 2 t mclk + 500 ns t ehel e high time 45 ns t e l el end of previous write (last e low) to e low for write cycle 2 t mclk t shsl as high time 30 ns C t rseh setup time of r - w_n to e high 30 ns C t sleh as low to e high 20 ns C t clsl cs_n low to as low 20 ns C t elch e low to cs_n high 0 ns C t copd clkout period (cd v is the value loaded in the clkout register representing the clkout divisor ) (cd v + 1) t osc t chcl clkout high period (cd v is the value loaded in the clkout register representing the clkout divisor ) (cd v + 1) ? t osc C 10 (cd v + 1) ? t osc + 15 a a Dread cycle without a previous write is where a read cycle follows a write cycle and where the falling edge of e for the write and the rising edge of e for the read are separated by at least 2 t mclk . ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 41 of 58 (888) 824 - 4184 figure 11 . mode 2 : general bus timing ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 42 of 58 (888) 824 - 4184 table 14 . mode 3 : asynchronous operation timing for 5.0v operation symbol par ameter minimum maximum 1/t xtal oscillator frequency 8 mhz 16 mhz 1/t sclk system clock frequency 4 mhz 10 mhz 1/t mclk memory clock frequency 2 mhz 8 mhz t avcl address or r - w_n valid to cs_n low setup 3 ns C t cldv cs_n low to data valid (for high - speed registers 02h, 04h, and 05h) 0 ns 55 ns cs_n low to data valid (for low - speed registers) read cycle without previous write a 0 ns 1.5 t mclk + 100 ns cs_n low to data valid (for low - speed registers) read cycle with previous write 0 ns 3.5 t mclk + 100 ns t kldv dsack0_n low to output data valid (for high - speed read registers) C 23 ns dsack0_n low to output data valid (for low - speed read registers) 0 ns C t chdv input data hold after cs_n high 15 ns C t chdh output data hold after cs_n high 0 ns C t chdz cs_n high to output data float C 35 ns t chkh 1 cs_n high to dsack0_n = 2.4v (a n on - chip pull - up will drive dsack0_n to approximately 2.4v; an external pull - up is required to drive this signal to a higher voltage ) 0 ns 55 ns t chkh 2 cs_n high to dsack0_n = 2.8v C 150 ns t chkz cs_n high to dsack0_n float 0 ns 100 ns t chcl cs_n width between successive cycles 25 ns C t chai cs_n high to address invalid 7 ns C t chri cs_n high to r - w_n invalid 5 ns C t clch cs_n width low 65 ns C t dvch cpu write data valid t o cs_n high 20 ns C t clkl cs_n low to dsack0_n low (for high - and low - speed registers) write cycle without previous write 0 ns 67 ns t chkl end of previous write (cs_n high) to dsack0_n low for a write cycle with a previous write b 0 ns 2 t mclk + 145 ns t copd clkout period (cd v is the value loaded in the clkout register representing the clkout divisor ) (cd v + 1) t osc t chcl clkout high period (cd v is the value loaded in the clkout register representing the clkout divisor ) (cd v + 1) ? t osc C 10 (cd v + 1 ) ? t osc + 15 a a Dread cycle without previous write is where a read cycle follows a write cycle and where the rising edge of cs_n for the write and the falling edge of cs_n for the read are separated by at least 2 t mclk . b a Dwrite cycle with a previo us write is a write cycle following a previous write cycle where the rising edge of cs_n for the first write and the rising edge of cs_n for the second write are separated by at least 2 t mclk . ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 43 of 58 (888) 824 - 4184 table 15 . mode 3 : asynchronous operation timing for 3.3v operation symbol parameter minimum maximum 1/t xtal oscillator frequency 8 mhz 16 mhz 1/t sclk system clock frequency 4 mhz 10 mhz 1/t mclk memory clock frequency 2 mhz 8 mhz t avcl address or r - w_n valid to cs_n low setup 3 ns C t cldv cs_n low to data valid (for high - speed registers 02h, 04h, and 05h) 0 ns 60 ns cs_n low to data valid (for low - speed registers) read cycle without previous write a 0 ns 1.5 t mclk + 100 ns cs_n low to data valid (for low - speed registers) read cycl e with previous write 0 ns 3.5 t mclk + 100 ns t kldv dsack0_n low to output data valid (for high - speed read registers) C 35 ns dsack0_n low to output data valid (for low - speed read registers) 0 ns C t chdv input data hold after cs_n high 15 ns C t chdh o utput data hold after cs_n high 0 ns C t chdz cs_n high to output data float C 35 ns t chkh 1 cs_n high to dsack0_n = 2.4v (a n on - chip pull - up will drive dsack0_n to approximately 2.4v; an external pull - up is required to drive this signal to a higher voltag e ) 0 ns 55 ns t chkh 2 cs_n high to dsack0_n = 2.8v C 150 ns t chkz cs_n high to dsack0_n float 0 ns 100 ns t chcl cs_n width between successive cycles 25 ns C t chai cs_n high to address invalid 7 ns C t chri cs_n high to r - w_n invalid 6.5 ns C t clch cs_n width low 65 ns C t dvch cpu write data valid to cs_n high 20 ns C t clkl cs_n low to dsack0_n low (for high - and low - speed registers) write cycle without previous write 0 ns 67 ns t chkl end of previous write (cs_n high) to dsack0_n low for a write cycle with a previous write b 0 ns 2 t mclk + 145 ns t copd clkout period (cd v is the value loaded in the clkout register representing the clkout divisor ) (cd v + 1) t osc t chcl clkout high period (cd v is the value loaded in the clkout register representing the clkout divisor ) (cd v + 1) ? t osc C 10 (cd v + 1) ? t osc + 15 a a Dread cycle without previous write is where a read cycle follows a write cycle and where the rising edge of cs_n for the write and the falling edge of cs_n for the read are separated by a t least 2 t mclk . b a Dwrite cycle with a previous write is a write cycle following a previous write cycle where the rising edge of cs_n for the first write and the rising edge of cs_n for the second write are separated by at least 2 t mclk . ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 44 of 58 (888) 824 - 4184 figure 12 . mode 3: asynchronous operation, read cycle ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 45 of 58 (888) 824 - 4184 figure 13 . mode 3: asynchronous operation, write cycle ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 46 of 58 (888) 824 - 4184 table 16 . mode 3 : synchronous operation timing for 5.0v operation s ymbol parameter minimum maximum 1/t xtal oscillator frequency 8 mhz 16 mhz 1/t sclk system clock frequency 4 mhz 10 mhz 1/t mclk memory clock frequency 2 mhz 8 mhz t ehdv e high to data valid (for high - speed registers 02h, 04h, and 5h) C 55 ns e high to data valid (for low - speed registers) read cycle without previous write a C 1.5 t mclk + 100 ns e high to data valid (for low - speed registers) read cycle with previous write C 3.5 t mclk + 100 ns t eldh data hold after e low for a read cycle 5 ns C t eldz da ta float after e low C 35 ns t eldv data hold after e low for a write cycle 15 ns C t aveh address and r - w_n to e setup 25 ns C t elav address and r - w_n valid after e falls 15 ns C t cveh cs_n valid to e high 0 ns C t elcv cs_n valid after e low 0 ns C t d vel data setup to e low 55 ns C t ehel e active width 100 ns C t avav start of a write cycle after a previous write access 2 t mclk C t avcl address or r - w_n to cs_n low setup 3 ns C t chai cs_n high address invalid 7 ns C t copd clkout period (cd v is the v alue loaded in the clkout register representing the clkout divisor ) (cd v + 1) t osc t chcl clkout high period (cd v is the value loaded in the clkout register representing the clkout divisor ) (cd v + 1) ? t osc C 10 (cd v + 1) ? t osc + 15 a a Dread cycle without previous write is where a read cycle follows a write cycle and where the falling edge of e for the write cycle and the rising edge of e for the read cy cle are separated by at least 2 t mclk . ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 47 of 58 (888) 824 - 4184 table 17 . mode 3 : synchrono us operation timing for 3.3v operation symbol parameter minimum maximum 1/t xtal oscillator frequency 8 mhz 16 mhz 1/t sclk system clock frequency 4 mhz 10 mhz 1/t mclk memory clock frequency 2 mhz 8 mhz t ehdv e high to data valid (for high - speed register s 02h, 04h, and 5h) C 60 ns e high to data valid (for low - speed registers) read cycle without previous write a C 1.5 t mclk + 100 ns e high to data valid (for low - speed registers) read cycle with previous write C 3.5 t mclk + 100 ns t eldh data hold after e low for a read cycle 5 ns C t eldz data float after e low C 50 ns t eldv data hold after e low for a write cycle 15 ns C t aveh address and r - w_n to e setup 25 ns C t elav address and r - w_n valid after e falls 15 ns C t cveh cs_n valid to e high 0 ns C t elcv cs_n valid after e low 0 ns C t dvel data setup to e low 55 ns C t ehel e active width 100 ns C t avav start of a write cycle after a previous write access 2 t mclk C t avcl address or r - w_n to cs_n low setup 3 ns C t chai cs_n high address invalid 7 ns C t copd clkout period (cd v is the value loaded in the clkout register representing the clkout divisor ) (cd v + 1) t osc t chcl clkout high period (cd v is the value loaded in the clkout register representing the clkout divisor ) (cd v + 1) ? t osc C 10 (cd v + 1) ? t osc + 15 a a Dread cycle without previous write is where a read cycle follows a write cycle and where the falling edge of e for the write cycle and the rising edge of e for the read cy cle are separated by at least 2 t mclk . ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 48 of 58 (888) 824 - 4184 figure 14 . mode 3: synchronous operation, read cycle timing ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 49 of 58 (888) 824 - 4184 figure 15 . mode 3: synchronous operation, write cycle timing ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 50 of 58 (888) 824 - 4184 table 18 . serial interface mode timing for 5.0v operation symb ol parameter minimum maximum sclk serial port interface clock 0.5 mhz 8 mhz t cyc 1/sclk 125 ns 2000 ns t skhi minimum clock high time 65 ns C t sklo minimum clock low time 65 ns C t lead enable lead time 70 ns C t lag enable lag time 109 ns C t acc acces s time C 60 ns t pdo maximum data out delay time C 59 ns t ho minimum data out hold time 0 ns C t dis maximum data out disable time C 665 ns t setup minimum data setup time 35 ns C t hold minimum data hold time 84 ns C t rise maximum time for input to go f rom v ol to v oh C 100 ns t fall maximum time for input to go from v oh to v ol C 100 ns t cs minimum time between consecutive cs_n assertions 670 ns C t copd clkout period (cd v is the value loaded in the clkout register representing the clkout divisor ) (cd v + 1) t osc t chcl clkout high period (cd v is the value loaded in the clkout register representing the clkout divisor ) (cd v + 1) ? t osc C 10 (cd v + 1) ? t osc + 15 ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 51 of 58 (888) 824 - 4184 table 19 . serial interface mode timing for 3.3v operation symb ol parameter minimum maximum sclk serial port interface clock 0.5 mhz 8 mhz t cyc 1/sclk 125 ns 2000 ns t skhi minimum clock high time 65 ns C t sklo minimum clock low time 65 ns C t lead enable lead time 70 ns C t lag enable lag time 109 ns C t acc acces s time C 60 ns t pdo maximum data out delay time C 59 ns t ho minimum data out hold time 0 ns C t dis maximum data out disable time C 665 ns t setup minimum data setup time 35 ns C t hold minimum data hold time 84 ns C t rise maximum time for input to go f rom v ol to v oh C 100 ns t fall maximum time for input to go from v oh to v ol C 100 ns t cs minimum time between consecutive cs_n assertions 670 ns C t copd clkout period (cd v is the value loaded in the clkout register representing the clkout divisor ) (cd v + 1) t osc t chcl clkout high period (cd v is the value loaded in the clkout register representing the clkout divisor ) (cd v + 1) ? t osc C 10 (cd v + 1) ? t osc + 15 ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 52 of 58 (888) 824 - 4184 figure 16 . serial interface mode: icp = 0 and cp = 0 figure 17 . serial interface mode: icp = 1 and cp = 1 ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 53 of 58 (888) 824 - 4184 6. innovasic part number cross - reference table 20 cross - references the current innovasic part number with the corresponding intel part number . table 20 . innovasic part number cross - reference innovasic part number intel part number package type temperature grades ia82527pqf44ar 2 (lead free C rohs) as82527 as82527f8 qe82527 44 - pin pqfp automotive ia82527plc44ar 2 (lead free C rohs) an82527 an82527f8 qx82527 tn 82527 en82527 44 - pin plcc automotive other packages and temperature grades may also be available. ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 54 of 58 (888) 824 - 4184 7. errata 7.1 summary errata no. problem version 2 part numbers ia82527pqf44ar2 ia82527plc44ar2 1 the cpu writes to msg box 15 ram cannot be read back if msgva l is set. exists 2 setting the intpnd bit to 1 from cpu interface will not cause interrupt. exists 3 an unintended remote frame may be generated. exists 4 majority logic sample mode delays start of ack bit transmission by one time quanta. exists 7.2 de tail errata no. 1 problem: the cpu writes to msg box 15 ram cannot be read back if msgval is set. description: if the msgval bit (bits [7 C 6]) of msg box 15 control_0 register (0xf0) is set, any cpu writes to the msg box 15 arbitration 0 C 3 registers (0xf 2 C 0xf5), and data 0 C 7 registers (0xf7 C 0xfe) will operate properly, however cpu reads of these registers will return unknown data. in other words, any cpu data written to msg box 15 will not be read back correctly if the msgval bit is set. if the msgval b it (bits [7 C 6]) of msg box 15 control_0 register (0xf0) is reset, cpu data written can be read back normally. workaround: the workaround is to clear the msgval bit (bits [7 C 6]) of msg box 15 control_0 register (0xf0) before trying to read back any cpu dat a written to the msg box 15 arbitration 0 C 3 registers (0xf2 C 0xf5), and data 0 C 7 registers (0xf7 C 0xfe). ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 55 of 58 (888) 824 - 4184 errata no. 2 problem: setting the intpnd bit to 1 from cpu interface will not cause interrupt. description: during normal operation, a can message e vent sets the intpnd bit of control 0 register of the appropriate message box (assuming appropriate interrupt enables are set), and the interrupt signal is asserted. the cpu will then reset intpnd to clear the interrupt. the errata issue occurs if the us er directly sets the intpnd bit via the cpu interface, no interrupt will be generated. workaround: none. errata no. 3 proble m: an unintended remote frame may be generated. description: if a message box is set to receive and a remote frame with a matching id and data length code (dlc) is received, the ia82527 will generate an unexpected remote frame for the id in the message box instead of just acknowledging the can message. a message box configured as follows may lead to this scenario, as expl ained below : 1. a message box is set with an id in the arbitration registers to match the id of remote frame. 2. the message box control_0 register has msgval(bits[7 - 6]) in the set state. 3. the message box control_1 register has all fields in the reset state. 4. the message box configuration register has the dir bit (bit 3) reset to 0 for receive. 5. the message box configuration register has the dlc field set to match the dlc of the remote frame. when the ia82527 sees a remote frame that matches the message box id and dlc, the ia82527 will generate the expected rx_ok status change interrupt . the ia82527 will also generate an unexpected rx interrupt for the message box that matches the id of the re mote frame if the rxie field of the message box control_0 register is in the set state. in addition, t he ia82527 will generate an unexpected remote frame for the id in the message box. workaround: in a system that uses remote frames, only use a singl e remote frame requester for a single remote frame responder. ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 56 of 58 (888) 824 - 4184 errata no. 4 problem: majority logic sample mode delays start of ack bit transmission by one time quanta. description: when the spl bit (bit 7) of the bit timing register 1 (0x4f) is set to 1 to enable the 3 sample majority logic mode, the transmission of the ack bit in response to a received can frame will be time shifted by 1 time quanta. with sufficient cable propagation delays and propagation delays through can transceiver parts, can nodes on the can bus may see the ack bit being a 0 shifted over into its ack delimiter bit time and flag this as an error. workaround: use single sample mode instead of majority logic sample mode. the spl bit of the bit timing register 1 (bit 7 of add ress 0x4f) should be a 0. ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 57 of 58 (888) 824 - 4184 8. revision history table 21 presents the sequence of revisions to document ia21108050 4 . table 21 . revision history date revision description page(s) august 12 , 2008 00 first edition released. na august 2 5 , 2008 01 errata no. 5 added . 49, 50 march 1 2, 2009 02 ia82527 - rev 2 part marking and cross reference information added ; errata no. 6 added . 48, 49, 51 march 27, 2009 03 updated plcc package dimensions 11 april 29, 2009 04 updated tables 3, 6, 10, 11 , 12, 14 to revise various ratings and descriptions ; updated errata section to remove errata associated with pre - production parts and to add one new errata . 21, 26, 34, 38, 40, 46, 49 , 50 june 1 , 2009 05 updated to include information for operation at 3.3 v , and added errata 4 . 6, 16, 26, 27, 33 - 51 , 54 - 56 sept. 16, 2009 06 corrected tables 5 and 7 regarding ambient temperature range. 25, 27 ia82527 data sheet can serial communications controller sep tember 16 , 200 9 ia 211080504 - 0 6 http://w ww.innovasic.com customer support: page 58 of 58 (888) 824 - 4184 9. for further information the innovasic semiconductor ia 82527 controller area network (can) serial communications con troller is a form , fit, and function replacement for the original intel ? 8 2527 serial communications controller . the innovasic support team wants our information to be complete, accurate, useful, and easy to understand. please feel free to contact our exp erts at innovasic at any time with suggestions, comments, or questions. innovasic support team 3737 princeton ne suite 130 albuquerque, nm 87107 (505) 883 - 5263 fax: (505) 883 - 5477 toll free: (888) 824 - 4184 e - mail: support@innovasic.com website: http://www.innovasic.com |
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